Digital IC Design Senior Staff / Staff / Senior Engineers (multiple headcounts)
Semiconductor MNC
Singapore, Singapore
4d ago

Description Position 1 : Senior Staff / Staff / Senior Digital IC Design Engineer IP Development (several headcounts) Responsibility :

  • Work on RTL design implementation and verification, this includes but not limited to Verilog RTL coding, logic synthesis, test bench development, RTL and gate level simulation / verification, code coverage, formal verification, test vector generation and design documentation. Requirements :
  • Bachelor Degree or above in Electronic Engineering
  • 6+ years of digital IC design experience
  • Good knowledge on digital VLSI design
  • Good knowledge and experience on Verilog RTL design, Verilog simulation and logic synthesis
  • Strong analytical and problem solving skills
  • Good verbal and communication skills Position 2 : Senior Staff / Staff / Senior Digital IC Design Engineer SoC Frontend Integration (several headcounts) Responsibility :
  • Responsible for all aspects of SoC chip development
  • Work on chip level design infrastructure
  • Integrating both internal and external IPs into SoC
  • Chip-level RTL design implementation
  • Chip-level logic synthesis
  • Interface with all disciplines : system architect, IP designers, analog Requirements :
  • Bachelor or Master Degree in Electronic Engineering
  • 6+ years of SoC design experience
  • Industry exposure to and knowledge of SoC design methodology, especially logic synthesis, static timing analysis, and logic equivalence check
  • Experience with system design methodologies that contain multiple clock domains
  • Experience in clock, power management and system debug designs is a plus
  • Experience in low-power design issues, tools, and methodologies highly desired
  • Excellent collaboration skills
  • Good communication and interpersonal skills
  • Strong analytical and problem-solving skills Position 3 : Senior Staff / Staff / Senior Digital IC Design Engineer Synthesis & STA (several headcounts) Responsibility :
  • Work on SoC Timing Closure.
  • This includes, but not limited to SoC timing constraints, SoC synthesis, clock tree synthesis, static timing analysis and timing closure

  • Work closely with physical design engineers to achieve timing closure Requirements :
  • Bachelor or Master Degree in Electronic Engineering
  • 6+ years of SoC design experience
  • Familiar with SoC design flow
  • Experience in full-chip synthesis, STA and timing closure
  • Experience in Verilog RTL coding
  • Experience in RTL and gate-level simulation / verification
  • Good communication and interpersonal skills
  • Strong analytical and problem-solving skills Country Singapore Company Semiconductor MNC Salary From US$50,000 Working Hours Full-
  • Time Contract Permanent Categories Electrical / Electronics / Instrumentation / Control Industries

    Apply
    Apply
    My Email
    By clicking 'Continue', I agree to neuvoo's Privacy & Terms and agree to receive relevant email job alerts. (cancel anytime) See here
    Continue
    Application form